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60HZclock
- 基于ATMEGA16的60HZ时钟发生器，ICCAVR工程，调试通过。-The 60HZ clock generator based on ATMEGA16, ICCAVR engineering, debugging through.
s1c33_uCos
- uCos在s1c33上的移植 S1C33 MCU EPSON最新的32位微处理器系列，专用于需要高级数据处理的便捷设备。 CPU性能 核心CPU 精工EPSON32位的RISC CPU，32位内部数据处理 33MHz 105条16位固定长度的指令 16个32位多用途的寄存器 在60MHZ操作下的最小指令执行时间为16.7ns 乘法、除法和MAC指令 内存 0~128K ROM 8K RAM 片内周边电路 晶振电路 32.769K~33MHz 定
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
shuzi
- 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时，显示满刻度为23时59分59秒，并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源，采用低功耗的芯片及液晶显示器，发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74，计数器采用同步双十进制计数器74LS160，锁存译码器是74LS248，整电报时电路用74LS74，74L
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
clock
- AVR 128 Signal Generator
40KHZtimer
- 该程序使用ATMEGA16单片机产生40KHZ时钟发生器。-The program generated using ATMEGA16 microcontroller 40KHZ clock generator.
sequencecontroller
- this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
VHDL
- 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register w
clock1
- 此为时钟发生器，可以进行即使或者什么的功能，至少我希望是这样的-This is a clock generator, or even what can be the function, at least I hope so
51Developer
- 1602和24C02芯片一起编写时钟发生器程序，1602主要用于显示，2402用于随时储存数据， 使得断电后数据能够保存 上电后能继续走动-1602 and 24C02 chip clock generator with the writing process, mainly for 1602 show that 2402 is used to store data at any time, so the data can be saved after power off after pow
ClckGen
- Clock generator, simple desin
ROM-based-sine-wave-generator-design
- 设计基于ROM的正弦波发生器，对其编译，仿真。 具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。-ROM-based sine wave generator design, its compilation, simulation. Specific requireme
alu_simulation
- VHDL alu unit design and simulation with RAM, ROM, clock generator and 2 simple programs to execute.
RISC_CPU
- VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator,
FDDDDSPLLP
- 一种基于FPGA的新的的DDS+PLL时钟发生器 -An FPGA-based new DDS+PLL clock generator
Sine-wave-generator
- 正弦波发生器，内有TESTBENCH文件，输出时钟和复位信号，用于仿真。用MEDELSIM仿真，然后仿真通过。-The sinewave generator within have TESTBENCH file output clock and reset signals for simulation. With MEDELSIM emulation, and simulation through.
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
icst
- This an almost identical implementation to the ICST525 clock generator. The s2div and idx2s files are different-This is an almost identical implementation to the ICST525 clock generator. The s2div and idx2s files are different
FT232RL
- 2005FT232R USB UART I.C. Incorporating Clock Generator Output and FTDIChip-ID™ Security Dongle-2005FT232R USB UART I.C. Incorporating Clock Generator Output and FTDIChip-ID™ Security Dongle